1. Field of the Invention
This invention relates to oscillation detection circuits for detecting oscillations of oscillation circuits such as crystal oscillators, and in particular relates to oscillation detection circuits for avoiding operation errors due to dispersions and variations of circuit constants of oscillation circuits.
2. Description of the Related Art
Conventionally, oscillation circuits are installed in electronic devices to produce oscillation signals, based on which electronic circuits operate. In order to guarantee operations of circuitry inputting output signals of oscillation circuits, it is necessary to detect whether or not oscillation circuits are placed in oscillated states. Therefore, oscillation detection circuits are conventionally used, and various examples of oscillation detection circuits using delay circuits have been disclosed in Japanese Unexamined Patent Publication No. Hei 10-190413, Japanese Unexamined Patent Publication No. 2000-122749, and Japanese Unexamined Patent Publication No. 2002-43906, for example.
Now, the configuration and operation of an oscillation detection circuit using a delay circuit will be described with reference to FIGS. 7A to 7E. FIG. 7A shows the configuration of an oscillation detection circuit which is conventionally known, wherein an input signal IN corresponds to an output signal of an oscillation circuit (not shown), which is supplied to a first input terminal of an exclusive-or circuit EO via an inverter IV and a delay circuit DL and is also supplied directly to a second input terminal of the exclusive-or circuit EO. An output terminal of the exclusive-or circuit EO is grounded via a capacitor CP and is also connected to an comparison circuit CM, which compares between a potential (or voltage) “O” at the output terminal of the exclusive-or circuit EO and a reference voltage REF, thus producing an output signal OUT. That is, when the potential O becomes lower than the reference voltage REF, the output signal OUT becomes high.
Next, the overall operation of the oscillation detection circuit will be described with reference to FIGS. 7A to 7E. Before starting oscillation, the input signal IN is fixed at a high level or a low level, wherein the exclusive-or circuit EO receives an delayed signal INB, which is delayed from the input signal IN by the delay circuit D1, in addition to the input signal IN. In this case, the input signal IN and the delayed signal INB differ from each other in level, regardless of the level of the input signal IN, which is either a high level or a low level. That is, the output signal O of the exclusive-or circuit EO is fixed to a high level, so that the capacitor CP is being charged. Therefore, the comparison circuit CM receives such a high-level output signal O to produce a low-level output signal OUT.
When oscillation is started in the aforementioned initial state so that an oscillation signal whose level is periodically changed is applied as the input signal IN, which is inverted by the inverter IV and is then delayed by a prescribed delay time in the delay circuit DL, which in turn outputs the delayed signal INB. In this case, there may alternately occur first periods in which both the input signal IN and the delayed signal INB match in level and second periods in which the input signal IN and the delayed signal INB differ from each other in level. That is, the exclusive-or circuit EO receiving the input signal IN and delayed signal INB produces the output signal O, which is set to a low level in first periods or which is set to a high level in second periods. For this reason, when the oscillation circuit is placed in an oscillated state, charging and discharging are alternately effected on the capacitor CP.
When a discharged value exceeds a charged value, the capacitor CP may be observed in a discharged state apparently, so that the output signal O of the exclusive-or circuit EO, which may differ from the foregoing level established before oscillation is started, becomes a low level. Therefore, by detecting such a low-level output signal O of the exclusive-or circuit EO, it is possible to detect whether or not oscillation circuit is placed in an oscillated state (or an oscillation mode). That is, by adequately adjusting the delay time of the delay circuit DL in advance, a prescribed timing relationship is established between the input signal IN and the delayed signal INB in such a way that the discharged value exceeds the charged value in the oscillation mode.
The comparison circuit CM compares between the level of the output signal O and the reference voltage REF, so that when the level of the output signal O becomes lower than the reference voltage REF, the comparison circuit CM produces the output signal OUT of a high level, based on which an oscillation mode is detected.
Thereafter, when oscillation is stopped so that the input signal IN is fixed to a low level, for example, the delayed signal INB output from the delay circuit DL is fixed to a high level. That is, there occurs an unmatched condition where the input signal IN and the delayed signal INB do not match in level. In such an unmatched condition, the exclusive-or circuit EO receiving the input signal IN and delayed signal INB operates to charge the capacitor CP, thus producing the output signal O of a high level. When the level of the output signal O exceeds the reference voltage REF, the comparison circuit CM produces the output signal OUT of a high level, based on which an oscillation stop mode is detected.
In the aforementioned oscillation detection circuit of FIG. 7A, the capacitor CP is placed in a discharged state using the delay circuit DL. Of course, it is not always required to use the delay circuit in placing the capacitor in a discharged state. That is, Japanese Unexamined Patent Publication No. Hei 11-220330 and Japanese Unexamined Patent Publication No. 2001-326565 disclose other examples of oscillation detection circuits, in which oscillation is detected under discharged states of capacitors not using delay circuits.
Next, an example of the aforementioned oscillation detection circuit for detecting oscillation under a discharged state of a capacitor not using a delay circuit will be described with reference to FIGS. 8A to 8E. FIG. 8A shows the configuration of an oscillation detection circuit in which an input signal corresponding to an output signal of an oscillation circuit (not shown) is supplied to a first input terminal of a logical circuit OR as a signal INA via an inverter IVA, and an integration circuit consisting of a resistor RA and a capacitor CA, and it is also supplied to a second input terminal of the logical circuit OR as a signal INB via a buffer circuit consisting of inverters IVB and IVC, and an integration circuit consisting of a resistor RB and a capacitor CB. Each of the inverters IVA and IVC may be constituted by a pair of MOS (Metal-Oxide Semiconductor) transistors of different polarities, i.e., an NMOS transistor for outputting a low level and a PMOS transistor for outputting a high level, wherein on-resistance of the NMOS transistor is set smaller than on-resistance of the PMOS transistor.
Next, the operation of the oscillation detection circuit of FIG. 8A will be described with reference to FIGS. 8B to 8E.
Before oscillation is started, one of the signal INA or the signal INB is fixed to a high level in response to the level of the input signal IN, while the other is fixed to a low level. Therefore, the logical circuit OR inputting the signals INA and INB produces an output signal OUT having a high level. Before oscillation is started, the input signal IN is placed in a low level, so that the signal INA is high, while the signal INB is low.
When oscillation is started in the initial condition described above, the input signal IN periodically changes the level thereof (see FIG. 8B), and the inverter IVA produces an inverted signal whose level is inverted compared with the input signal IN. The inverted signal is then subjected to integration in the integration circuit consisting of the resistor RA and the capacitor CA. As described above, the inverter IVA is constituted by a pair of MOS transistors of different polarities, wherein on-resistance of one transistor outputting a low level is set smaller than on-resistance of the other transistor; therefore, the rise of the signal INA becomes sharp while the decay (or trail) of the signal INA becomes dull. For this reason, the signal INA that is initially set to a high level may repeatedly rise and fall in level thereof, so that it will be gradually reduced to a low level (see FIG. 8C).
The output signal of the inverter IVC that depends on the input signal IN is subjected to integration in the integration circuit consisting of the resistor RB and the capacitor CB, thus producing the signal INB. As described above, the inverter IVC is constituted by a pair of MOS transistors of different polarities, wherein on-resistance of one transistor outputting a low level is set smaller than on-resistance of the other transistor; therefore, the rise of the signal INB becomes sharp while the decay (or trail) of the signal INB becomes dull. For this reason, the signal INB may be substantially maintained at a low level while it repeatedly rises and falls in level thereof.
According to the aforementioned oscillation detection circuit of FIG. 8A, after the oscillation circuit starts oscillation, both the signals INA and INB are substantially placed in a low level, so that the logical circuit OR produces the output signal OUT of a low level. Thereafter, when oscillation is stopped so that the input signal is fixed to a high level, for example, the signal INA is fixed to a low level while the signal INB is fixed to a high level (see FIG. 8D), so that the logical circuit OR produces the output signal OUT of a high level. In summary, the output signal OUT of the logical circuit OR is maintained in a low level during an oscillation mode in which the oscillation circuit continuously performs oscillation. Thus, it is possible to detect oscillation in response to the level of the output signal OUT.
In the oscillation detection circuit of FIG. 7A, it is necessary to properly set the delay time of the delay circuit DL and to reduce dispersions of time constants for determining the rise time and decay time of the signal within a prescribed range. Otherwise, the oscillation detection circuit may have difficulties in detecting oscillation, which may cause a reduction of yield in production of circuits.
The aforementioned problem will be described in more detail with reference to FIGS. 9A to 9I, wherein each of time periods TA represents a matched condition where both the signals IN and INB match each other in level so that the capacitor CP is being discharged, and each of time periods TB represents an unmatched condition where the signals IN and INB do not match each other in level so that the capacitor CP is being charged. FIGS. 9A to 9C show an example in which both the time periods TA and TB are identical to each other, wherein a charged value and a discharged value are equal to each other in the capacitor CP. In this example, the average value of the level of the signal O output from the exclusive-or circuit EO is stabilized and is set to an intermediate value between the source voltage and the ground potential, so that the signal O is not set to a low level, which makes oscillation detection inoperable. FIGS. 9D to 9F show an example in which the time period TA is shorter than the time period TB, wherein a discharged value is smaller than a charged value in the capacitor CP. In this example, the signal O is maintained in a high level and is not reduced to a low level, which makes oscillation detection inoperable as well.
FIGS. 9G to 9I show an example in which the time period TA is longer than the time period TB, wherein a discharged value is greater than a charged value. Therefore, during the oscillation mode of the oscillation circuit in progress, the signal O is gradually reduced to a low level, which makes oscillation detection operable.
As described above, the operability of oscillation detection greatly depends upon a relationship between the discharged value and charged value of the capacitor CP, which in turn depends upon various factors such as the delay time of the delay circuit DL, and time constants for determining the rise time and decay time of the signal O. Therefore, it is necessary to properly adjust these factors.
However, if the delay time of the delay circuit DL is greatly varied or if the time constants are greatly varied due to dispersions of on-resistances of transistors constituting the exclusive-or circuit EO, there may occur an undesired situation where the discharged value does not exceed the charged value. This makes oscillation detection inoperable, which may cause a reduction of yield in production of circuits.
The aforementioned oscillation detection circuit of FIG. 8A may have a similar problem, wherein both the signals INA and INB are not simultaneously placed in a low level due to unexpected dispersions of on-resistances of transistors constituting the inverters INA to INC, in other words, either one of the signals INA and INB may be unexpectedly placed in a high level. This makes oscillation detection inoperable.